Today, the increasing need to store more and more information has resulted in the fact that Static Random Access Memories (SRAMs) occupy the greatest part of a System-on-Chip (SoC). Therefore, SRAM's robustness is considered crucial to guarantee the reliability of such SoCs over lifetime. In this context, one of the most important phenomena degrading nano-scale SRAMs reliability is related to Negative-Bias Temperature Instability (NBTI). This paper proposes a new approach based on an On-Chip Aging Sensor (OCAS) to detect SRAM aging during system lifetime. The sensor is able to detect any specific aging state of a cell in the SRAM array. The strategy is based on the connection of an OCAS per SRAM column, which periodically performs off-line testing by monitoring write operations into the SRAM cells to detect aging. The approach is application-transparent since it is does not change the SRAM contents after testing. To prevent OCAS from aging by one side and from dissipating static power by the other side, OCAS circuitry is powered-off during idle periods. SPICE simulations in a 65nm CMOS technology demonstrate the high sensor sensitivity to detect early aging states and so, guarantying high memory reliability. Furthermore, area overhead due to sensor insertion is almost negligible.