Abstract:
Clock networks are composed of buffers and flip-flops that are susceptible to Single Event Transient (SET) faults. Therefore, it is important to evaluate in terms of SET ...Show MoreMetadata
Abstract:
Clock networks are composed of buffers and flip-flops that are susceptible to Single Event Transient (SET) faults. Therefore, it is important to evaluate in terms of SET vulnerability when designing radiation-hardened circuits. For that, we developed an automatic method of extraction of clock network parameters from any ASIC design layout to allow a more precise SET propagation analysis by electrical simulations. We analyzed the clock tree network from SRAM arbiter layout using the proposed methodology and we found that the most vulnerable nodes in the clock tree are the output of the smaller buffers and nodes with lowest fan-out.
Published in: 2012 13th Latin American Test Workshop (LATW)
Date of Conference: 10-13 April 2012
Date Added to IEEE Xplore: 06 August 2012
ISBN Information:
Print ISSN: 2373-0862