The main reason to invest in 3D circuits adoption is the possibility of decrease the wire length, replacing horizontal wires by shorter vertical through-silicon-vias (called of TSVs). As a consequence, a better performance is expected and other optimizations also can be obtained in comparison with planar technology. In relation to 3D circuits, the networks-on-chip (NoCs) receiving special attention because they are very used to provide efficient communication with wide parallelism. However, the development of 3D circuits is not trivial, being very common appear imperfections and manufacture problems, mainly in sensitive regions as the TSVs. Thus, the main contribution of this work is to allow the usability of the NoC in 3D circuits even in the presence of multiple defective TSVs, with minimal impact on the latency results. In this way, the behavior of the routing algorithm called Elevator-First, to tolerate defective TSVs, will be analyzed. In order to provide an appropriated alternative path to forward the traffic flow in the presence of multiple faulty TSVs, the use of traffic flow monitors has been proposed. The results obtained for the considered scenarios of simulation prove that the strategy can be very efficient, shown that is possible to improve more than 50% of latency in relation to the original algorithm evaluated without traffic flow analysis.