The power density of integrated circuits increases with the technology scaling, so the need of implementing low-power designs is increasing. The clock gating technique is typically employed to reduce the dynamic power consumption in digital integrated circuits. However, the use of this approach could affect the reliability of the device in the presence of soft errors caused by radiation. The objective of this work is to propose a methodology in order to find the susceptibility to single event effects of clock-gated designs using the standard design flow for standard cell ASIC. A novel fault injection structure was developed for clock-gated flip-flops. A case study 10-bit counter circuit is used to apply the proposed methodology. Gate-level simulations are performed for the analysis of susceptibility, using the generated netlist along with the delays extracted from the logic synthesis.