In this paper, authors propose two approaches of fault injection emulation performed in the configuration memory bits of an SRAM-based FPGA. One is based on exhaustive and sequential fault injection and the other one is based on random accumulated distribution of fault occurrence. The goal is to present the difference between these two approaches and how the random approach, that is significantly faster than the exhaustive one, can be used to well estimate the susceptibility and reliability of a design synthesized into an SRAM-based FPGA.