Dynamic Voltage and Frequency Scaling is the most commonly used power managment techinique in modern processors. However, the ability of an individual chip to operate under reduced supply voltage can no longer be predetermined at the design stage and may even change over time. This paper presents Cyclic Power-Gating (CPG), a novel power management strategy where the power consumption of a core can be finely controlled without scaling the supply voltage. CPG builds on state-retentive power-gating which allows the power supply to a core to be switched off and on again at high speed (tens of clock cycles) with minimal disruption to running programs. The power-gating is cyclic, by altering the ratio of time spent powered-on and off in each power-gating period the effective operating frequency and power consumption of a core can be controlled. The overheads in delay and power consumption of CPG for an out-of-order core in a 14 nm technology are accurately modelled and compared to the performance and power consumption of Voltage/Frequency pairs in the same technology. The proposed power gating method reduces average power consumption by 4 percent over voltage and frequency scaling with only a 2 percent degradation in performance.