ARSENAL: Architecture for Secure Non-Volatile Memories | IEEE Journals & Magazine | IEEE Xplore

ARSENAL: Architecture for Secure Non-Volatile Memories


Abstract:

Whereas data persistence in non-volatile memories (NVMs) enables instant data recovery (IDR) in the face of power/system failures, it also exposes NVMs to data confidenti...Show More

Abstract:

Whereas data persistence in non-volatile memories (NVMs) enables instant data recovery (IDR) in the face of power/system failures, it also exposes NVMs to data confidentiality and integrity attacks. Counter mode encryption and Merkle Tree authentication are established measures to thwart data confidentiality and integrity attacks, respectively, in NVMs. However, these security mechanisms require high overhead atomic security meta-data updates on every write-back in order to support IDR in NVMs. This increases memory traffic and negatively impacts system performance and memory lifetime. Architecture for Secure Non-Volatile Memories (ARSENAL) is an IDR-preserving, low cost, high performance security solution that protects NVM systems against data confidentiality and integrity attacks. ARSENAL synergistically integrates (i) Smart Writes for Faster Transactions (SWIFT), a novel technique to reduce the performance overhead of atomic security meta-data updates on every write-back, with (ii) Terminal BMT Updates (TBU), a novel BMT-consistency-preserving technique, to facilitate IDR in the face of power/system failures. Our evaluations show that on average, ARSENAL improves system performance (measured in IPC) by 2.26× (4×), reduces memory traffic overhead by 1.47× (1.88×), and improves memory lifetime by 2× (3.5×) in comparison to conventional IDR-preserving 64-bit (128-bit) encryption+authentication.
Published in: IEEE Computer Architecture Letters ( Volume: 17, Issue: 2, 01 July-Dec. 2018)
Page(s): 192 - 196
Date of Publication: 06 August 2018

ISSN Information:

Funding Agency:


Contact IEEE to Subscribe

References

References is not available for this document.