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A Scalable and Efficient In-Memory Interconnect Architecture for Automata Processing | IEEE Journals & Magazine | IEEE Xplore

A Scalable and Efficient In-Memory Interconnect Architecture for Automata Processing


Abstract:

Accelerating finite automata processing benefits regular-expression workloads and a wide range of other applications that do not map obviously to regular expressions, inc...Show More

Abstract:

Accelerating finite automata processing benefits regular-expression workloads and a wide range of other applications that do not map obviously to regular expressions, including pattern mining, bioinfomatics, and machine learning. Existing in-memory automata processing accelerators suffer from inefficient routing architectures. They are either incapable of efficiently place-and-route a highly connected automaton or require an excessive amount of hardware resources. In this paper, we propose a compact, low-overhead, and yet flexible in-memory interconnect architecture that efficiently implements routing for next-state activation, and can be applied to the existing in-memory automata processing architectures. We use SRAM 8T subarrays to evaluate our interconnect. Compared to the Cache Automaton routing design, our interconnect reduces the number of switches 7×, therefore, reduces area overhead for the interconnect. It also has faster row cycle time because of shorter wires and consumes less power.
Published in: IEEE Computer Architecture Letters ( Volume: 18, Issue: 2, 01 July-Dec. 2019)
Page(s): 87 - 90
Date of Publication: 09 April 2019

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