We propose a hardware technique for cache coherence over the existing approaches that ensure that shared and less frequently used cache blocks bypass private caches of multiple cores. Furthermore, this manuscript proposes a mechanism to tune the aggressiveness of a data prefetcher. Increased cache hit rate and improved performance have been observed since coherence management and prefetching delays are avoided using the proposed bypassing and thread progress-aware prefetch controlling mechanism. Our approach shows around 19% improvement in cache hit rate and 29% average performance improvement over existing state-of-the-art techniques for Parsec & Splash-2 multithreaded benchmarks.