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CollectiveHLS: Ultrafast Knowledge-Based HLS Design Optimization | IEEE Journals & Magazine | IEEE Xplore
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High-Level Synthesis (HLS) has democratized FPGAs by enabling high-level device programmability and rapid microarchitecture customization using directives. Nevertheless, ...

Abstract:

High-level synthesis (HLS) has democratized field programmable gate arrays (FPGAs) by enabling high-level device programmability and rapid microarchitecture customization...Show More

Abstract:

High-level synthesis (HLS) has democratized field programmable gate arrays (FPGAs) by enabling high-level device programmability and rapid microarchitecture customization through the use of directives. Nevertheless, the manual selection of the appropriate directives, i.e., the annotations included in the high-level source code to instruct the synthesis process, is a difficult task for programmers without a hardware background. In this letter, we present CollectiveHLS, an ultrafast knowledge-based HLS design optimization method that automatically extracts the most promising directive configurations and applies them to the original source code. The proposed optimization scheme is a fully data-driven approach for generalized HLS tuning, as it is not based on quality of result models or meta-heuristics. We design, implement, and evaluate our method with more than 100 applications of Machsuite, Rodinia, and GitHub on a ZCU104 FPGA. We achieve an average geometric mean speedup of x14.1 and x10.5 compared to the unoptimized, i.e., without HLS directives and optimized designs, a high design feasibility score, and an average inference latency of 38 ms.
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High-Level Synthesis (HLS) has democratized FPGAs by enabling high-level device programmability and rapid microarchitecture customization using directives. Nevertheless, ...
Published in: IEEE Embedded Systems Letters ( Volume: 16, Issue: 2, June 2024)
Page(s): 235 - 238
Date of Publication: 07 November 2023

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