Extended transistor scaling has brought us a lot of benefits, but also a myriad of problems, including severe reliability issues [1]. To extend the scaling path as far as possible, system architects and technologists have to work together. They have to find solutions—e.g., at system level—to realize self-healing chips, chips that can detect or “feel” where errors occur and that know how to deal with them or in a way “cure” them. Only then will it be feasible to design systems in technologies with transistors scaled down to 5 nm dimensions.