Abstract:
This work aims to predict bounds on bit-error-rate performance of highspeed interconnects. The novelty lies in the characterization of timing jitter to achieve more accur...Show MoreMetadata
Abstract:
This work aims to predict bounds on bit-error-rate performance of highspeed interconnects. The novelty lies in the characterization of timing jitter to achieve more accurate modeling of such interconnects.
Published in: IEEE Design & Test ( Volume: 36, Issue: 1, February 2019)