This paper covers details of the Common Power Format (CPF) standard which is used for expressing power intent for IC design to minimize power consumption. It presents the key underlying concepts in the standard, such as, power domains and power nodes. It provides a simple example to show how power intent is expressed. It then discusses how power intent can be expressed in a layered manner to cover the entire design process as well as support for hierarchy in design. It elaborates on how IC's are designed using CPF and touches on key aspects of interoperability with the IEEE1801 low power standard.