This paper presents a novel time register circuit suitable for time-based or time-domain signal processing. The proposed circuit is based on the capacitor discharging method and is compensated against technology process and chip temperature variations using a novel calibration loop based on master-slave approach. The loop contains a high-speed comparator based on simple current-starved inverter logic along with a triple-point threshold voltage stabilization loop. The circuit is designed using 28nm Samsung FD-SOI process under 1V supply voltage with 10MHz operating frequency. Simulation results present an almost constant capacitor voltage discharging slope of the time register over worst case process corners and temperature between 0°C and 100°C while consuming only 10μA.