This paper describes a tool suite aimed at Functional Verification (FV) teaching in the context of VLSI circuits. FV is considered a major bottleneck in design cycles and one of the reasons is the lack of proper training. Therefore teaching it at the undergraduate or graduate levels is an important issue. This paper presents VEasy and describes the features that allow for lint analysis, simulation, data generation by a Graphical User Interface, checking and coverage collection and analysis. All these features merge together to create a complete verification environment, which is appropriated for teaching several concepts of FV.