A design methodology for constructing a high-frequency (30 to 40 GHz) fractional-N synthesizer in a 65 nm TSMC CMOS process is presented. The method is focused on minimizing the phase noise at the output of the synthesizer while achieving the desired frequency range and frequency resolution. The method involves selecting initial values for each PLL component, simulating each using a transistor-level simulation, i.e. Spectre, and deriving a noise and linearity model of operation. Using an initial guess for the loop filter transfer function, together with a set of Verilog-A models for the various PLL components, the loop filter transfer function is adjusted so that the output phase noise behaviour is minimized. If the noise performance does not meet specifications, noise and linearity bounds on the individual PLL components can be derived. These, in turn, will force the re-design of all or some of the PLL components. The approach described here has been used to design a fractional-N synthesizer in the frequency range of 30 - 40 GHz with 5 MHz frequency steps having a phase noise of less than -90 dBc/Hz at a 1000 kHz frequency offset.