This paper demonstrates the effectiveness and robustness of amplifier finite gain bandwidth compensation within a wideband third order continuous time delta sigma modulator and the effects of process, mismatch and temperature on modulator stability. In many state of the art designs, GBW is kept safely above the sampling frequency of the modulator, which suffers a power penalty especially for high-speed designs. While gain errors and phase shifts in the loop filter due to finite GBW can be compensated for, its robustness is often questionable, especially if an additional excess loop delay is concerned. The robustness of such a compensation is analyzed for an exemplary CT DSM with an f_S of 500MHz which has been designed in a 1.2V 90nm TSMC CMOS process. Therefore, the amplifiers are compensated for finite GBW values of 500 MHz, 300MHz and 600 MHz, and all three parasitic extracted amplifiers are analyzed over PVT. The simulated modulator performance of 72 dB SNDR over a 25MHz bandwidth is only degraded by 2 dB over corner simulations. In comparison to Monte Carlo analysis of all amplifiers, this reveals a modulator robustness to amplifier finite GBW as much as ±35% over process and mismatch, which emphasizes the feasibility of the approach.