This paper presents a design methodology for a low-frequency oscillator which consists of a current-starved (CS) voltage-controlled oscillator (VCO) and a frequency divider. The frequency divider is used to reduce frequency in an area efficient manner; achieving this by scaling up the sizes of VCO components is impractical for low frequency applications. We derive a model for the effective capacitance of a CSVCO so that design tradeoffs between area, power, and phase noise can be readily explored. The methodology supports optimization over these performance metrics, with adjustable weighting factors that emphasize their relative importance. Design examples in 0.5μm CMOS technology with 3.3 V supply are presented.