This paper presents a new asynchronous binary search analog to digital converter (ADC). Proposed asynchronous binary search ADC enables higher speed operation of binary search algorithm by resolving two bits in each step. Using two bit flash quantizers in each stage of the proposed binary search ADC the conversion speed improves by two times compared with conventional binary search ADC architectures. New sampling scheme and dynamic offset cancellation technique for the comparator have been adapted to realize a low power and high speed converter. The proposed single channel 6-bit 1GS/s ADC was designed in 65nm CMOS process. Simulation results show that the ADC reaches a peak SNDR of 36.12dB consuming 1.35mW from a single 1.2V power supply. It achieves of 29fJ/conv.code FoM.