Algorithm and VLSI architecture of channel estimation impaired by impulsive noise in PLC | IEEE Conference Publication | IEEE Xplore

Algorithm and VLSI architecture of channel estimation impaired by impulsive noise in PLC


Abstract:

In this paper, we investigate the channel estimation algorithm for medium-voltage, long haul power line communi-cation (PLC) system in the IEEE 1901 standard. To improve ...Show More

Abstract:

In this paper, we investigate the channel estimation algorithm for medium-voltage, long haul power line communi-cation (PLC) system in the IEEE 1901 standard. To improve the overall performance, we employ a dual Gaussian interpolation method working on the amplitude and phase domain simultane-ously, a major difference from the conventional schemes using the real and imaginary part. Meanwhile, to mitigate the effect of impulsive noise, a notorious impairment in PLC transmission, we propose an impulsiveness detection/cancellation method using unused null subcarriers. Extensive simulation results indicate improved performance than the conventional inter-polators in an impulsive environment. The channel models proposed by the open power-line communication European research alliance (OPERA) are utilized for simulation. The hardware architecture is also presented together with its achievable performance.
Date of Conference: 04-07 August 2013
Date Added to IEEE Xplore: 02 December 2013
Electronic ISBN:978-1-4799-0066-4

ISSN Information:

Conference Location: Columbus, OH, USA

References

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