The design of a pipelined SCL 8051 ALU is elaborated. Two versions of SCL gates are considered for gate-level implementation: SCL gates with both nsleep and sleep signals and SCL gates without nsleep signal. In both versions all combinational blocks, registers, and completion components can be put to sleep mode. In addition, the problem associated with pipelining the SCL 8051 ALU is explained and a solution is provided. The non-pipelined and pipelined SCL 8051 ALUs, implemented with both versions of SCL gates, are then simulated in transistor-level and compared in terms of area, speed, leakage power, dynamic power, and energy per operation. The SCL 8051 ALUs implemented with SCL gates without nsleep signal are shown to outperform the ones using the other gate style except for leakage power. In addition, it is shown that pipelining may have adverse effect on throughput.