In this paper we present the design of a Nyquist rate VCO based ADC implemented in 65nm CMOS process. The design achieves a peak SNDR of 63.7dB and a SFDR of 76dB in 10MHz bandwidth while consuming 1.1mW of power and occupying only 0.07mm² of active area. The pseudo-differential VCO implemented in the prototype achieves better than 9-bits linearity with the overall ADC linearity better than 12 bits. The figure of merit (FoM) is 44fJ/conversion and should improve when implemented in more advanced processes.