Advance in technology nodes of IC fabrication has introduced increased variation. This presents new challenges for delay testing. To address this challenge, speed-binning based on on-chip delay sensor measurements has been proposed as alternative to current speed-binning methods. This practice requires advanced data analysis techniques for the binning result to be accurate. In this paper, based on experiments with silicon data collected from on-chip delay sensors in a commercial design using a sub-65 nm process, we demonstrate that optimizing sensor selection can benefit speed-binning accuracy. An optimization algorithm is presented, and result showed it is capable of improving accuracy beyond 93%.