High Efficiency Video Coding (HEVC) standard uses Discrete Cosine Transform (DCT) to compress energy. The minimum and the maximum Transform Unit (TU) size used in HEVC is 4 × 4 and 32 × 32, respectively. With large TU size coding efficiency improves. But, it is at the cost of increased hardware complexity. Further, achieving full hardware utilization and constant throughput is a challenging task. In this paper, 8 point DCT expressions are tweaked to obtain 4 point DCT equations. As a consequence, it is possible to compute either two 4 point or one 8 point DCT operation using the same architecture. Additionally, constant throughput is achieved and memory utilization is increased by 25%. The proposed architecture is implemented on FPGA platform. The 1D DCT architecture operates at 183.3 MHz, whereas 2D DCT architecture works at 145.1 MHz. This entails that the proposed 2D DCT architecture can process 46 fps of UHD (3840 × 2160) video.