Recent papers have demonstrated that graph-based methodologies for supergate design can provide solutions with fewer transistors when compared to the widely used factoring methods. However, there is not enough discussion about the impact of those solutions on physical design, and it is important since the generated supergates have some special topological particularities. In this paper, we perform the layout design of this kind of supergate, inspecting some geometrical aspects Experiments made on a well-known catalogue of functions have demonstrated that the solutions produced by this graph-based approach have several optimizations concerning area, number of contacts and wirelength when compared to the cells generated through a state-of-art Boolean factoring methodology.