High-Efficiency Video Coding (HEVC) is the current video coding technique proposed by MPEG and ITU jointly. HEVC uses variable size Discrete Cosine Transform (DCT) for spatial redundancy and this paper presents a high throughput DCT architecture for the same. Reconfigured Multiple Constant Multiplication (RMCM) technique is introduced in this paper to realize constants used in the DCT operation. Throughput of the proposed architecture remains constant irrespective of the transform unit size. The proposed architecture is implemented on FPGA platform and the maximum frequency of operation of the 1D DCT architecture is 96.75 MHz. When used in 2D folded structure, it is possible to process 124 fps of 4k video and 31 fps of 8k video using this architecture.