Formal modeling and verification for pre-charge half buffer gates and circuits | IEEE Conference Publication | IEEE Xplore
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Formal modeling and verification for pre-charge half buffer gates and circuits

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Ashiq A. Sakib; Scott C. Smith; Sudarshan K. Srinivasan
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Abstract:

A formal modeling and verification methodology for Pre-Charge Half Buffer (PCHB) gates and circuits is presented. PCHB gates have hysteresis and incorporate a handshaking...Show More

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Abstract:

A formal modeling and verification methodology for Pre-Charge Half Buffer (PCHB) gates and circuits is presented. PCHB gates have hysteresis and incorporate a handshaking protocol. Thus, we model gates as transition systems and provide correctness property templates that capture safety and liveness. The methodology is demonstrated using several circuits.
Published in: 2017 IEEE 60th International Midwest Symposium on Circuits and Systems (MWSCAS)
Date of Conference: 06-09 August 2017
Date Added to IEEE Xplore: 02 October 2017
ISBN Information:
Electronic ISSN: 1558-3899
DOI: 10.1109/MWSCAS.2017.8052974
Conference Location: Boston, MA, USA
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