Abstract:
Gate-all-around nanowire transistor is deemed as one of the most promising solutions that enables continued CMOS scaling. Compared with FinFET, it further suppresses shor...Show MoreMetadata
Abstract:
Gate-all-around nanowire transistor is deemed as one of the most promising solutions that enables continued CMOS scaling. Compared with FinFET, it further suppresses short-channel effects by providing superior electrostatic control over the channel. Due to the unique device structure, gate-all-around nanowire transistor also allows more efficient layout design by exploiting 3-dimensional stacking configurations. In this paper, we investigate the 6T SRAM cell design for gate-all-around nanowire transistors using a device-circuit co-optimization framework. At the device level, TCAD simulation and current source modeling method are applied to extract the model. Layout designs with horizontal, lateral, vertical stacking device structures are explored. At the circuit level, read and write assist techniques are studied to relieve the negative impact of low on-currents on SRAM stabilities incurred by nanowire channels. Operating at 300 mV, assist techniques can increase the read static noise margin and the write static noise margin of 6T SRAM up to 82% and 92%, respectively.
Date of Conference: 06-09 August 2017
Date Added to IEEE Xplore: 02 October 2017
ISBN Information:
Electronic ISSN: 1558-3899