This paper presents a static non-linearity correction technique exemplary applied on a 10-bit source series terminated digital-to-analog converter (DAC) implemented in 180 nm CMOS. The proposed technique proves for the first time, that an undesired power supply and package resistance can be turned into a benefit by canceling non-linearity effects introduced by the MOSFET switches within the source series terminated DAC cell. To verify the proposed technique, first of all a simplified parametric model of an N-bit source series terminated DAC is developed, considering the non-linear MOSFET switch impedance as well as both parasitic on- and off-chip supply resistances. The presented analytical model proves the linearisation mechanism effect of the supply resistance counteracting the nonlinear switch on-resistance, thanks to its degeneration effect. The obtained results from mathematical model were verified by detailed circuit simulations. The gained simulation results correlate very well with the calculated INL values. Hence confirming the linearisation potential of the supply resistance to improve the overall DAC integral non-linearity. Specifically, for a supply resistance of 2.8 Ω the INL error of the realized DAC has a value of <;0.01 LSB.