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PAOA: A power and area optimization approach of reed-muller logic circuits | IEEE Conference Publication | IEEE Xplore

PAOA: A power and area optimization approach of reed-muller logic circuits


Abstract:

To find the best polarity of large-scale Mixed Polarity Reed-Muller (MPRM) logic circuits, this paper proposes a new Adaptive Simulated Annealing Genetic Algorithm (ASAGA...Show More

Abstract:

To find the best polarity of large-scale Mixed Polarity Reed-Muller (MPRM) logic circuits, this paper proposes a new Adaptive Simulated Annealing Genetic Algorithm (ASAGA) which can effectively find out the best polarity. Genetic Algorithm (GA) has outstanding global searching ability but easily falls into the local optimum, while the Simulated Annealing Algorithm (SAA) is expert in local searching but has the limitation of poor convergence. The new method incorporating SAA into GA is proposed which can play their strengths to the utmost extent and makes up their shortcomings. Additionally, for the key parameters of ASAGA, we adopt self-adaptive adjustment, which can effectively improve the convergence and robustness of the algorithm. The results proved the efficiency and accuracy of ASAGA in searching the best polarity of large-scale MPRM logic circuits.
Date of Conference: 06-09 August 2017
Date Added to IEEE Xplore: 02 October 2017
ISBN Information:
Electronic ISSN: 1558-3899
Conference Location: Boston, MA, USA

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