This paper proposes a digital design method enabling a constant path delay across temperature and process corners in 40nm CMOS. Thus, timing analysis and logic synthesis is simplified significantly. The temperature dependency is eliminated by operating at the zero temperature coefficient supply voltage. Additionally, process corner adaptive body biasing compensates process corner dependent path delays. Extensive transistor level simulations for various standard cells show constant path delays across temperature and 6σ process corners. All applied body bias voltages lie within the transistor reliability. This method enables rapid digital synthesis without time consuming process and temperature analyses and optimization.