This paper presents a linearization technique for differential transconductors in fully depleted silicon-on-insulator (FD-SOI) CMOS technology. Dynamic self-biasing is employed at the back-gate node thereby compensating the non-linearity of the main differential input pair. The method yields excellent linearity beyond 85 dBc under a considerable input voltage 1 Vppd and is highly applicable in high-bandwidth and wide-swing GmC based Sigma-Delta converters. The basic principle of the linearization is introduced and proven in a complex ADC architecture. Transistor level simulations show a linearity improvement of 25 dB while only increasing the loop filters power dissipation by 10 %. Process corner, temperature as well as mismatch dependency is evaluated proving the concepts robustness and efficiency.