Developing hardware-efficient and high-speed BLAKE256 hardware has recently been a research trend because BLAKE256 is today an important hash function for maintaining the security of blockchain networks, such as Decred and HyperCash. However, existing BLA KE-256 circuits still have low performance and hardware efficiency. Therefore, this paper proposes the BLAKE256 accelerator to achieve high performance and hardware efficiency for securing the blockchain networks. To achieve those goals, the proposed BLAKE-256 accelerator has three novel optimization techniques. First, a fully unrolled datapath architecture is proposed to generate one hash per clock cycle, thus improwing the performance. Second, a pipelined arithmetic-logic unit (ALL) is proposed to shorten the critical path. Third, nonce generating and checking block mechanisms (NGB and NCB) are developed to reduce the data transfer time between the CPU and the accelerator, which can improve the total processing rate Based on our experiments on a Xilinx Zynq UltraScale+ MPSoC ZCU102 FPGA at the system-onchip level, the impact of proposed optimization techniques is clearly proven. Moreover, experimental results on several FPGAs show that our proposed accelerator has significantly better throughput and area efficiency than previous BLAKE-256 architectures.