This paper presents a power-efficient CMOS Image Sensor (CIS) with in-sensor computation and in-pixel gain calibration. The CIS can output $32\times 32$ image or directly process the image in-sensor with analog domain computation. The output of the CIS is sampled by an array of 8bi Single Slope ADC (SS ADC). This CIS features extra low power consumption with highly configurable parameters. Convolution can be done in-sensor with a power efficiency of $131.7\mathrm{nJ}/$ frame. To suppress the gain fluctuation, a bulk-modulation technique is introduced. The overall gain variation is reduced by 15% in the worst condition. The whole system is designed and simulated in 180nm standard CMOS process. To verify the soundness of the system, the first layer of a 4bit Quantized Neural Network (QNN) on the MNIST dataset is replaced by the proposed CIS. Result shows that the CIS can work under 120fps and the accuracy of the system only decreases by 1.7% compared to the software. The overall power consumption is only $15.9\mu\mathrm{W}$, which is greatly smaller than the digital approach.