A new low-power, high-precision inverter-based CMOS comparator is introduced in this paper. Inherent high-power consumption of CMOS inverter is controlled by a current-limiting circuit. A current-modulation technique is proposed to maximize the gain of the comparator before making its decision. The comparator uses two unfolded inverters and a sampling circuit to complete its operation. The current-modulation circuit uses a programmable current mirror and a 5-bit counter without adding much power to the original circuit. An auxiliary comparator and a reference generator are implemented to control the current modulation operation. The circuit presented addresses the gain error resulting from charge injection in the inverter and corrects the error arising from incorrect reset operation. The circuit was simulated in a standard 180nm CMOS process. Simulations show up to 3x improvement of the comparator's gain with very high precision. Only one calibration circuit is required for any number of comparators; hence, this technique can be used to achieve high-resolntion ADCs.