Sub-crosspoint RRAM decoding for improved area efficiency | IEEE Conference Publication | IEEE Xplore

Sub-crosspoint RRAM decoding for improved area efficiency

Publisher: IEEE

Abstract:

Two sub-crosspoint physical topologies are proposed that places the decode circuitry beneath the metal-oxide RRAM crosspoint array. The first topology integrates only the...View more

Abstract:

Two sub-crosspoint physical topologies are proposed that places the decode circuitry beneath the metal-oxide RRAM crosspoint array. The first topology integrates only the row decode circuitry, while the second integrates both the row and column decoder. The topology for sub-crosspoint row decoding reduces area by up to 38.6% over the standard peripheral approach, with an improvement in area efficiency of 21.6% for small arrays. Sub-crosspoint row and column decoding reduces the RRAM crosspoint area by 27.1% and improves area efficiency to nearly 100%.
Date of Conference: 08-10 July 2014
Date Added to IEEE Xplore: 21 August 2014
Electronic ISBN:978-1-4799-6384-3

ISSN Information:

Publisher: IEEE
Conference Location: Paris, France

References

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