As of today, the semiconductor industry has been looking for possible alternative materials of silicon, since the physical limitation of silicon-based devices, i.e., planar CMOS devices for most of the scenarios, is approaching soon. Among all the novel materials arising from the horizon, graphene is considered to be a very promising alternative for its unique electrical properties. Although all kinds of prospective electrical properties it has(e.g., high mobility), there are barriers for Graphene-based Field Effect Transistors (G-FETs) to overcome, in order to find its way to the substitution of Silicon Metal Oxide Semiconducting Field Effect Transistors (Si-MOSFETs). One of the most important engineering barriers to be overwhelmed is the parasitic parameters, among which the parasitic resistance is considered to be one of the most critical roadblock. Contact resistance in G-FETs is relatively high compared to that of conventional Si-MOSFETs. In this paper, we present an experimental demonstration of a new method to reduce the contact resistance in back gate G-FETs. In the proposed device structure, the source/drain regions are fabricated using multilayer graphene (MLG), thus the top and edge contacts are formed between the MLG and metal electrodes, while the conducting channel is still formed by using single-layer graphene (SLG). Due to the high conductivity of MLG and relative low conductivity of SLG, the contact resistance is reduced while the controllability of channel conductivity is preserved.