A sparse-iteration 4D CORDIC (COordinate Rotation DIgital Computer) has recently been developed for multiplying hypercomplex numbers one of which is a constant coefficient. This novel solution allows for implementing area-efficient quaternion multipliers in ASIC and FPGA. This paper shows how to extend the sparse-iteration CORDIC circuit so as to allow it to compute various products related to one coefficient: to left- or right-multiply a variable by a given quaternion or its conjugate. It is demonstrated that such switching requires only marginal delay and area overheads, while versatile hardware multipliers are very useful in transform-type algorithms.