This paper proposes a synthesizable successive approximation register analog to digital converter (SAR ADC) that consists of only standard cells. In this SAR ADC, analog components such as resistive digital to analog converters (RDAC), a four-input clocked comparator, and track and hold (T/H) circuits are fully implemented with standard cells. The layout of the analog components is implemented with automatic place and route, which drastically relaxes the design burden and time. The prototype is fabricated in a 65 nm standard CMOS technology with 0.0053 mm² area occupation. The measurement results show that SNDR and SFDR are 28.1 dB and 32.5 dB respectively, at 10 MS/s sampling rate with 4.99 MHz sinusoidal input.