In this paper, we study the propagation of timing error in a synchronous All-Digital Phase-Locked Loop network. The architecture of the network represents a linear array of oscillators, where the first oscillator is considered as the reference oscillator, and the others are implemented as digitally controlled oscillators. The synchronisation of the network is achieved through interactions between a controlled oscillator and its closest neighbours. Using FPGA prototyping, we have shown that the jitter of a controlled oscillator saturates with the distance from the reference oscillators and that the bidirectional topology has better performance than the unidirectional topology. A comparison of measurements with a theoretical model is carried out to verify our FPGA prototyping framework.