High-speed wireless communication in the post-5G era will likely make use of frequency bands above 100 GHz. This poses challenges to IC design in silicon technologies. This paper presents a general comparison of a D-band transformer-based Class-AB power amplifier with cross-coupled capacitive neutralization in three advanced silicon technologies: bulk CMOS, fully-depleted SOI, and SiGe BiCMOS. Each of these technologies has its own prospects and disadvantages. A comparison of performance parameters is made such as the maximum available power gain G_max, saturation power P_sat, drain efficiency DE and power added efficiency PAE after properly sizing the transistors to reach an optimum load resistance Ropt. Further, a 140 GHz 4-stage power amplifier is fabricated in a 28 nm bulk CMOS process as a reference. Its design considerations, layout parasitics analysis, and layout techniques are discussed as well.