This paper presents the design and characterization of a unique low-power pulsewidth demodulator (PWDM) which works by controlling the total amount of charge stored on a capacitor. The proposed PWDM consists of a time-to-voltage converter (TVC) and a flash architecture based 2-bit analog-to-digital converter (ADC). The TVC operates in two phases: the charge phase and the discharge phase. During the charge phase an input pulsewidth-modulated (PWM) signal charges a capacitor to a certain value. The larger the width of the PWM signal, the higher the voltage developed across the charged capacitor. This capacitor voltage, which is unique to each pulsewidth, is then digitized inside a 2-bit ADC. During the discharge phase, the capacitor is allowed to completely discharge to ground. Designed in the 45-nm RFSOI CMOS, the PWDM occupies an active area of 70 × 80 μm², achieves data rates upto 8 Gb/s, and dissipates only 7.25 mW of power. To the best of the authors' knowledge, the proposed PWDM offers the best energy figure compared to the existing pulsewidth demodulator designs.