A 16bit 125Msps pipelined analog-to-digital converter (ADC) critical front-end stage supporting variable input common-mode voltage in 0.18um CMOS process is designed in this paper. The difference between the common-mode voltage of the input signal and the one of the reference causes the summing node of the residue amplifier to deviate from the appropriate voltage. To make the ADC support wide input common-mode voltage from 0.6V to 1.3V, the common-mode refreshing technique is proposed. The summing node is floating when the method is employed. To make the amplifier not disturbed and recover quickly, the dynamic biasing technique is applied to turn off the amplifier when the system is in the sampling phase. Offset calibration is employed in the sub-ADC to reduce comparator’s offset. The designed ADC achieves 90.7 dBc spurious-free dynamic range (SFDR), 79.5 dBFS signal-to-noise-and-distortion ratio (SNDR) under 70MHz input signal with 0.8V input common-mode voltage. The ability of supporting wide input common-mode voltage is proven by simulation.