Long range, low latency wireless links in Networks-on-Chip (NoCs) have been shown to be the most promising solution to provide high performance intra/inter-chip communication in many core era. Significant advancements have been made in design of both Wireless NoC (WNoC) topologies and transceiver circuits to support wireless communication at chip level. However, a comprehensive understanding of wireless physical layer and its impact on performance is still lacking. There is still a lot of scope for thorough analysis of the affects of intra-chip wireless channel and antenna characteristics on signal transmission and link reliability in WNoCs. To this end, we analyse signal propagation through wireless channel by accurately modelling the intra-chip environment. We analyse the effects of antenna placement across chip plane and its directionality on the signal loss, delay and dispersion properties. The analysis shows that directional antenna exhibits better delay characteristics, while omnidirectional antennas have low loss for signal transmission in the channel. Furthermore, the placement of antenna shows considerable impact on channel characteristics due to reflections from chip edges and constructive or destructive interference between the multiple signal components. This work provides crucial insights into propagation characteristics of on-chip wireless links for better design of transceiver components and their performance.