In this work we propose a variant of double-tail latched comparator, designed in 22 nm FDSOI (fully depleted silicon on insulator), operating at 2.88 GHz with supply voltage 0.8 V and achieving input referred offset and rms noise of 2.38 mV (1σ) and 33 µV, respectively in post-layout simulations. By modifying the timing control of the conventional double-tail comparator, the gain of the pre-amplifier is increased, thereby enhancing the speed, noise and offset parameters of the comparator.