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VLSI integration of a RO-based PUF into a 65 nm technology | IEEE Conference Publication | IEEE Xplore

Abstract:

Ring Oscillator Physical Unclonable Functions (ROPUFs) take advantage of process variability during the manufacturing process to exploit the small differences in the RO o...Show More

Abstract:

Ring Oscillator Physical Unclonable Functions (ROPUFs) take advantage of process variability during the manufacturing process to exploit the small differences in the RO oscillating frequencies and generate unique identifiers (ID). Its structure makes it suitable for, both, FPGA and ASIC applications. This paper presents a RO-PUF implementation using a semi-custom design methodology in TSMC 65 nm technology which has been validated through the entire design process, manufactured and experimentally characterized. Results show a good performance and robustness against temperature and voltage variations while obtaining up to three bits from each execution to generate digital IDs.
Date of Conference: 29-30 October 2024
Date Added to IEEE Xplore: 18 November 2024
ISBN Information:
Conference Location: Lund, Sweden

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