Abstract:
In this paper, 3D NAND floating gate (FG) and charge trap (CT) cell fundamentals, advantages and challenges are discussed. Future scaling options and associated challenge...Show MoreMetadata
Abstract:
In this paper, 3D NAND floating gate (FG) and charge trap (CT) cell fundamentals, advantages and challenges are discussed. Future scaling options and associated challenges from fabrication process integration, equipment engineering is briefly presented. The low string current (Istr) and threshold voltage (VT) variability challenge from polycrystalline silicon (poly-Si) channel is a key device technology challenge for 3D NAND scaling. This paper discusses about the physics of poly-Si channel, its challenges and improvement options in detail. Finally, this paper presents the alternative channel material requirements, options and 3D NAND scaling outlook.
Published in: 2018 Non-Volatile Memory Technology Symposium (NVMTS)
Date of Conference: 22-24 October 2018
Date Added to IEEE Xplore: 06 January 2019
ISBN Information: