Synthesis of low-cost parity-based partially self-checking circuits | IEEE Conference Publication | IEEE Xplore

Synthesis of low-cost parity-based partially self-checking circuits


Abstract:

A methodology for the synthesis of partially self-checking multilevel logic circuits with low-cost parity-based concurrent error detection (CED) is described. A subset of...Show More

Abstract:

A methodology for the synthesis of partially self-checking multilevel logic circuits with low-cost parity-based concurrent error detection (CED) is described. A subset of the inputs of the circuit is selected to realize a simple characteristic function such that CED is disabled whenever the inputs belong to the OFF-set of the characteristic function. This don't-care space in the operation of the CED circuitry is used to optimize the CED circuitry during synthesis. It is shown that this methodology is very effective at targeting faults with a high sensitization probability. Experimental results show that the proposed approach, which is of special interest in applications where a low-cost CED solution is desired, achieves a significant reduction in the error rate in logic circuits.
Date of Conference: 07-09 July 2003
Date Added to IEEE Xplore: 22 July 2003
Print ISBN:0-7695-1968-7
Conference Location: Kos, Greece

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