The abstraction level of designing digital circuits is rising since high-level synthesis tools are gaining acceptance and are available from different vendors. Simultaneously, the demand for accurate energy estimations on higher abstraction levels is increasing. But estimating energy on these abstraction levels is a difficult task since switching capacitances and area depend on scheduling and allocation decisions which are made during high-level synthesis. In this paper a current energy estimation methodology is extended by a power estimation approach to enable energy-aware design designs on behavioural level. The energy estimation uses control-flow information to model energy and runtime of a component while the power estimation approach generates power and protocol state machines by monitoring external port behaviour and putting it in relation to power dissipation. The methodology is evaluated for a linear predictive coding algorithm receiving its input data from a memory block which is provided as a black-box IP-component. By using the presented estimation methodology, it can be decided at behavioural level whether the usage of this memory element violates a given power budget. The average estimation error for energy is 12.55% while runtime can be estimated with an error of 1.5%.