Memory built in self repair (BISR) is gaining importance since several years. New fault tolerance approaches are mandatory to cope with increasing defect levels affecting memories produced with current and upcoming nanometric CMOS process. This problem will be exacerbated with nanotechnologies, where defect densities are predicted to reach levels that are several orders of magnitude higher than in current CMOS technologies. This work presents an evaluation of the area cost and yield of BISR architectures addressing memories affected by high defect densities. Statistical fault injection simulations were conducted on several memories. The obtained results show that BISR architectures can be used for future high defect technologies, providing close to 100% memory yield, by means of reasonable hardware cost.